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ds04-22415-1e fujitsu semiconductor data sheet assp communication control cmos scsi-ii protocol controller (with single-ended driver/receiver) MB86604l n description the fujitsu MB86604l is a single-ended transmission type scsi-ii protocol controller (spc) with a single-ended driver/receiver. the MB86604l facilitates interface control between small/medium host computer and peripheral devices (such as a hard disk and printer). the specifications conform to the scsi-ii standard. the MB86604l supports high-speed synchronous transfer, the mpu/dma independent system data bus, and user programmable command set to enable configuration of high-performance systems. it can also have the phase-to-phase sequence control function to reduce the program overhead of the host mpu. the MB86604l incorporate with a single-ended type scsi driver/receiver which can drive 48 ma of large-current, and so, the device can be directly connected with the scsi bus. the device can operate with +5 v single-power supply and in up to 40 mhz clock frequency. as for package, a 100-pin plastic small quad flat package is available. n features scsi bus interface: ? conforming to the scsi-ii standard ? operatable as initiator and target (continued) n pac k ag e 100 pin, plastic lqfp (fpt-100p-m05)
2 MB86604l (continued) ? two types of high-speed data transfer: C synchronous data transfer (max. 10 mbytes/s, max. 32 offsets, 32-step transfer rate) C asynchronous data transfer (max. 5 mbyte/s) ? transfer parameters (transfer mode, transfer rate, transfer offset) can be set for up to 7 connected devices. ? single-ended transmission type (maximum cable length: 6 m): C on-chip single-ended driver/receiver which can drive 48 ma of "l" level output current C directly connectable with the scsi bus ? on-chip three-state bidirectional i/o buffers for scsi req and ack pins (db7 -db0 , dbp , atn , msg , c/d , i/ o pins can be selected from either three-state or open-drain buffer by controlling the test pins input.) transfer operation: ? automatic response to selection/reselection (preset receiving operation can perform at the selection/ reselection.): C initiator: automatically operates until message received without command issue. C target: automatically operates until command received without command issue. ? automatic receiving: C initiator: automatically receives information for new phase to which target transited without command issue. C target: automatically receives message from initiator when initiator generates attention condition. ? on-chip 32-byte data register (fifo) for data phase ? on-chip two (send-only and receive-only) 32-byte data buffers for message, command, and status phases ? on-chip 16-bit transfer block register and 24-bit transfer byte register enabling 1 tbytes transfer (1 tbytes: 16 mbytes 64 k blocks) ? on-chip independent data transfer bus enabling the mpu operation during the data transfer ? parity through/generate can be specified. system bus interface: ? 8-bit or 16-bit separate mpu and dma buses ? directly connectable with a 80 series or 68 series mpu ? two types of transfer operation: C program transfer C dma transfer (burst/handshake) command set: ? supports sequential commands and programmable commands in addition to ordinary commands ? command queuing (command can be continuously issued by putting tags to commands in command phase.) ? on-chip 256-byte memory for command programming memory and command queuing buffer others ? process: cmos process ? supply voltage: single +5 v ? input system clock: 20 mhz/30 mhz/40 mhz ? package: 100-pin plastic lqfp
3 MB86604l n pin assignment index 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 bhe udp d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 v ss d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ldp cs 1 v ss v dd cs 0 a4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 wr rd v dd v ss clk reset int mode dbp v ss db 7 db 6 db 5 v dd v ss v ss db 4 db 3 db 2 db 1 v ss db 0 test 1 tmout a3 a2 a1 a0 atn v ss bsy ack rst v ss v ss v dd msg sel c/d req v ss i/o test2 tp v ss v dd dreq dack (fpt-100p-m05) i owr i ord v dd v ss dma 0 ldmdp dmd 0 dmd 1 dmd 2 dmd 3 dmd 4 dmd 5 dmd 6 dmd 7 v ss dmd 8 dmd 9 dmd 10 dmd 11 dmd 12 dmd 13 dmd 14 dmd 15 udmdp dmbhe (open) (open) (top view)
4 MB86604l n pin description 1. scsi interface * : regarding the status of information transfer which is indicated by msg , c/d , and i/o pins, see table phase status. pin number symbol pin name i/o function 60 req request i/o transfer request signal in the information transfer phases from target to initiator. the input signal to this pin is used for the timing control of data transfer sequence. this is a three-state i/o pin and an active low pin. 68 ack acknowledge i/o this pin is for the acknowledge signal from initiator to target for the req signal in the information transfer phases. the input signal to this pin is used for the timing control of data transfer sequence. this is a three-state i/o pin and an active low pin. 71 atn attention i/o this pin is for the attention signal that initiator requests target for the message transfer phase. this is an active-low pin. 63 msg * message i/o this pin is for the message signal that specifies type of information transferred on the data bus. this is an active-low pin and becomes l when message phase is specified. 61 c/d * control/data i/o this pin is for the control/data signal that specifies type of information transferred on the data bus. this an active-low pin and becomes l level when command, status, or message phase is specified. 58 i/o * input/output i/o this pin is for the input/output signal that specifies direction of information transferred on the data bus. this is an active-low pin. when this pin is l level, the information is transferred from target to initiator. when this pin is h level, the information is transferred from initiator to target. 69 bsy busy i/o this pin is for the scsi bus busy signal. in the arbitration phase, this is for the request signal for the use of bus acquisition. this is an active-low pin. 62 sel select i/o this pin is for the select signal used by initiator to select target during the selection phase and by target to reselect initiator during the reselection phase. this is an active-low pin. 67 rst reset i/o this pin is for the reset signal used by any device on the bus. when the device is an input operation, the reset signal is input to this pin. when output operation, the reset signal is output from this pin. this is an active-low pin. 11, 12, 13, 17, 18, 19, 20, 22 db7 to db0 data bus 7 to data bus 0 i/o these pins are for the bidirectional 8-bit scsi data bus and 1-bit odd parity line. 9dbp data bus parity
5 MB86604l note: the scsi interface input/output pins can be connected to a single-end type scsi bus. 2. mpu interface (continued) phase name msg c/d i/o transfer direction initiator target data-out phase h h h ? data-in phase h h l ? command phase h l h ? status phase h l l ? message-out phase l l h ? message-in phase l l l ? pin number symbol* pin name i/o function 77 cs0 chip select 0 i this is a chip select 0 pin used by mpu to select the spc as an i/o device. this is an active-low pin. 80 cs1 chip select 1 i this is a chip select 1 pin to select when mpu inputs/outputs the data on dma bus through spc. this is an active-low pin. 98, 97, 96, 95, 94, 93, 92, 91 d15 to d8 data 15 to data 8 i/o these pins are for the upper byte and parity bit of mpu data bus. when the cs0 input is valid, these pins serve as i/o ports for the spc internal registers. when the cs1 input is valid, these pins serve as i/o ports for the dma bus data. 99 udp upper data parity 89, 88, 87, 86, 85, 84, 83, 82 d7 to d0 data 7 to data 0 i/o these pins are for the lower byte and parity bit of the mpu data bus. when the cs0 input is valid, these pins serve as i/o ports for the spc internal registers. when the cs1 input is valid, these pins serve as i/o ports for the dma bus data. 81 ldp lower data parity 76, 75, 74, 73, 72 a4 to a0 address 4 to address 0 i these are address input pins to select the spc internal registers. 2rd (r/w ) read (read/write) i in the 80-series mode, this is a read signal input pin (iord or rd ) that mpu reads the spc. this read signal pin is an active- low. in the 68-series mode, this pin functions as the control signal input (r/w) to control the read/write operation to the spc. in the read operation, this pin is an active-high. in the write operation, this pin is an active-low. 1wr (lds ) write (lower data strobe) i in the 80-series mode, this pin is a write signal input pin (iowr or wr ) that mpu writes to the spc. this write signal input pin is active-low. in the 68-series mode, this pin function as the lower data strobe signal input (lds ) that mpu outputs when the lower byte of data bus is valid. the lds pin is an active-low.
6 MB86604l (continued) * : the pin symbols in parenthesis are the ones when the mode input is l. 3. dma interface (continued) pin number symbol* pin name i/o function 100 bhe (uds ) bus high enable (strobe) i in the 80-series mode, this pin is used for input of the bus high enable signal (bhe ) output from the mpu when the upper byte of the data bus is valid. the bhe pin is an active-low. in the 68- series mode, this pin functions as the upper data strobe signal input pin (uds ) output from the mpu when the upper byte of the data bus is valid. the uds pin is also an active-low. 7int (int ) interrupt request o the int and int pins are the interrupt request signal output. the int pins is used for the 80-series mode (an active-high pin), and the int signal is used for the 68-series mode (an active-low pin). 8 mode mode i this input pin is used to select the type of the mpu and dma buses. in the 80-series mode, a high level is input. in the 68- series mode, a low level is input. pin number symbol* pin name i/o function 52 dreq dma request o this is an output pin of dma transfer request signal to the dma controller. the data transfer between the spc and memory via the dma bus is requested. this pin is an active-high. 51 dack dma acknowledge i this is a dma acknowledge signal input pin output from the dma controller that enables the dma transfer. this pin is an active-low. when this pin is an active state, the dma cycle (read/ write) is valid. 48, 47, 46, 45, 44, 43, 42, 41 dmd15 to dmd8 dma data 15 to dma data 8 i/o these pins are the input/output pins of the upper byte and parity bit of the dma data bus. when the signal input to the cs1 pin (pin 80) is valid, these pins are connected directly to the mpu data bus. 49 udmdp upper dma data parity 39, 38, 37, 36, 35, 34, 33, 32 dmd7 to dmd0 dma data 7 to dma data 0 i/o these pins are the input/output pins of the lower byte and parity bit of the dma data bus. when the cs1 (pin 80) input is valid, these pins are connected directly to the mpu data bus. 31 ldmdp lower dma data parity 27 iord (dmr/w ) i/o read (dma read/ write) i in the 80-series mode, this pin (iord or rd ) is used for the input pin to output the data from the spc to the dma bus. this is an active-low pin. in the 68-series mode, this pin functions as a control signal input pin (dmr/w ) to input/output the data to the spc by the dma controller. in the output operation, this pin is on the high-state (active-high state). in the input operation, this pin is on the low-state (active-low state). 26 iowr (dmlds ) i/o write (dma lower data strobe) i in the 80-series mode, this (iowr or wr ) is used for the input pin to input the dma bus data to the spc. in the 68-series mode, this pin functions as a dma lower data strobe input (dmlds ) that dma controller outputs when the lower byte of the dma bus data is valid. both iowr and dmlds pins are an active-low.
7 MB86604l (continued) * : the pin symbols in parenthesis are the ones when the mode input is l. 4. others * : the pin symbols in parenthesis are the symbols when the mode input is l. pin number symbol* pin name i/o function 50 dmbhe (dmuds ) dma bus high enable (dma upper data strobe) i in the 80-series mode, this pin is for the dma bus high enable signal input pin (dmbhe ) output from the dma controller when the upper byte of the dma data bus is valid. this is an active-low pin. in the 68-series mode, this pin functions as the dma upper data strobe signal input pin (dmuds ) output from the dma controller when the upper byte of data bus is valid. the dmuds pin is also an active-low. 30 dma0 dma address 0 i in the 80-series mode, this pin is used for the dma address 0 input pin output from the dma controller. in the 68-series mode, a high level should be input to this pin. 55 tp transfer permission i this is a dma transfer permission signal input pin. when this pin is in active-state, the spc does the dma transfer. in case that this pin becomes inactive during the dma transfer, the dma transfer is paused on the block boundary. this pin is an active high. pin number symbol* pin name i/o function 6 reset reset i system reset input pin. the input reset active pulse width must have 4 times of the clock cycle at least. this is an active-low pin. 5 clk clock i clock signal input pin. 20 mhz, 30 mhz, or 40 mhz can be applied as the input clock frequency. 3, 14, 28 53, 64, 78 v dd power supply +5 v power supply pins. 4, 10, 15 16, 21, 29 40, 54, 59 65, 66, 70 79, 90 v ss ground ground pins. 23 test1 test i this pin is used to select the type of i/o buffer on scsi data bus pins. in case that dbp , db7 C db0 pins are used as an open- drain i/o, connect this pin to v ss . in case of three-state i/o, connect to v dd . 57 test2 test i this pin is used to select the type of i/o buffer on scsi pins. in case that msg , c/d , i/o , and atn pins are used as an open- drain i/o, connect this pin to v ss . in case of three-state i/o, connect to v dd . 24 tmout timeout o this is a scsi timeout pin that indicates the spc has been busy longer than the specified time. a high level is output on this pin if the spc busy time exceeds the specified time. this pin can be used for the timeout counter. 25, 26 (open) (open) these are open pins. those pins are not connected with the device internally. those pins must be left open.
8 MB86604l n block diagram dreq dack dmbhe dma0 dmd15 to dmd8 udmdp dmd7 to dmd0 ldmdp iowr iord tp msg c/d i/o atn bsy sel rst req ack db7 to db0 dbp tmout int wr rd cs0 cs1 a4 to a0 bhe mode d15 to d8, udp d7 to d0, ldp mpu interface internal processor timer registers phase controller transfer controller scsi interface data register (32 bytes) command user program memory (256 bytes) send mcs buffer (32 bytes) receive mcs buffer (32 bytes) dma interface
9 MB86604l n block description 1. international processor (sequencer) performs sequence control between the scsi bus phases. 2. timer manages the scsi time standards. also, conducts the following time managements. ? time until the req or ack signal is asserted for asychronous transfer data ? time until selection or reselection is retried ?req and ack timeout time during transfers: asychronous transfer case target: after the req is asserted, the time until the initiator asserts the ack initiator: after the ack is asserted, the time until the target negates the req synchronous transfer case target: after the req is sent, the time until an ack signal which makes the offset 0 is received from the initiator ? spc timeout manages the spc timeout indicating the spc busy time longer than the specified time. 3. phase controller controls the various phases executed by scsi such as arbitration, selection/reselection, data in/out, command, status, and message in/out. 4. transfer controller controls the information (data, command, status, message) transfer phases executed by scsi. the following two types of transfer phases are used. asychronous transfer: controls interlock (response confirmation format) between the req and ack signals. synchronous transfer: controls a maximum 32-byte offset value for the data in or data out phase. the following two modes exist for the data phase. program transfer: uses data register (address 00/01) via the mpu interface dma transfer: uses dreq and dack signals via the dma interface. the transfer parameter setting values for synchronous transfer (transfer mode, transfer rate, transfer offset) can be strobe for individual id device and are automatically established when the data phase is initiated. the number of transfer bytes is defined as block length number of blocks. bus free phase arbitration phase selection phase information transfer phase information transfer phase: ? command phase ? data phase ? status phase ? message phase
10 MB86604l 5. register the main registers are listed. ? command register command is specified by an 8-bit code. specifies the program head address assigned to the user program memory for user program applications. ? chip status register shows the chip's operating state, nexus counterpart id, and data register state. ? scsi bus status register shows the scsi control signal state. ? interrupt status register shows 8-bit code. ? command step register shows 8-bit code indicating the command execution state. error analysis can be performed by referring to the information in this register and the interrupt status register. ? group 6/7 command length setting register sets the group 6/7 command length which is undefined by the scsi standard. by setting the command length in this register, the spc can determine the command length. 6. receive-mcs buffer a receive only, 32-byte data buffer which stores information received via scsi (message, command, status) m: message, c: command, s: status 7. send-mcs buffer a send only, 32-byte data buffer which stores information sent via scsi (message, command, status) 8. command user program memory program memory used for establishing programmable commands (256 bytes). 9. data register fifo-type data register which stores data in scsi data phase (32 bytes).
11 MB86604l n absolute maximum ratings (see warning) * : v ss = 0 v warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions *1: v ss = 0 v *2: scsi pins are db7 to db0 , dbp , bsy , sel , rst , atn , req , ack , msg , c/d , i/o note: the recommended operating conditions are the values recommended to ensure correct logic operation of the lsi. the standard values of the electrical characteristics (dc and ac characteristics) are guaranteed within the range of the recommended operating conditions. parameter symbol rating unit min. max. power supply voltage* v dd v ss C 0.5 6.0 v input voltage* v i v ss C 0.5 v dd + 0.5 v output voltage* v o v ss C 0.5 v dd + 0.5 v operating ambient temperature top C25 +85 c storage temperature tstg C40 +125 c parameter symbol value unit min. typ. max. power supply voltage * 1 v dd 4.75 5.0 5.25 v h level input voltage * 1 clk v ih 3.5 v except scsi and clk pins 2.2 v scsi pins 2.0 v l level input voltage * 1 clk v il 1.5v except clk pin 0.8 v h level output current * 2 except scsi pins i oh C2.0 ma scsi pins three-state C8.0 ma open-drain ma l level output current * 2 except scsi pins i ol +3.2ma scsi pins +48 ma operating ambient temperature ta 0 +70 c
12 MB86604l n electrical characteristics 1. dc characteristics (v dd = +5 v5%, v ss = 0 v, ta = 0 c to +70 c) *1: scsi pins are db7 to db0 , dbp , bsy , sel , rst , atn , req , ack , msg , c/d , i/o note: leakage current in the above spec indicates the following currents. (1) leakage current at the high-z state on the three-state output pins. (2) leakage current at the output high-z state (input state) on the bidirectional bus pins. parameter symbol condition value unit min. max. h level input voltage clk v ih 3.5 v except scsi and clk pins 2.2 v scsi pins 2.0 v l level input voltage clk v il 1.5 v except clk pin 0.8 v input hysteresis of scsi pins * 1 v hw 0.3v h level output voltage * 1 except scsi pins v oh i oh = C2.0 ma 4.2 v dd v scsi pins three-state i oh = C8.0 ma 2.0 v open-drain v l level output voltage * 1 except scsi pins v ol i ol = +3.2 ma v ss 0.4 v scsi pins i ol = +48.0 ma 0.5 v input leakage current i li v ss v i v dd C10 +10 m a input/output leakage current i loz v ss v i v dd , see note below C10 +10 m a power supply current i dd all output pins opened clk input = 20 mhz spc operating clock = 10 mhz 45 ma clk input = 30 mhz spc operating clock = 10 mhz 48 ma clk input = 40 mhz spc operating clock = 13.3 mhz 55 ma clk input = 30 mhz spc operating clock = 15 mhz 65 ma clk input = 20 mhz spc operating clock = 20 mhz 60 ma clk input = 40 mhz spc operating clock = 20 mhz 70 ma
13 MB86604l 2. i/o pin capacitance (v dd = v i = 0 v, f = 1 mhz, ta = +25 c) 3. load conditions for ac characteristics (v dd = +5 v5%, v ss = 0 v, ta = 0 c to +70 c) parameter symbol value unit min. max. input pin capacitance c in 6pf output pin capacitance c out 6pf i/o pin capacitance except scsi pins c i/o 6pf scsi pins 25 pf r l1 = 110 w load resistance r l2 = 165 w load capacitance r l = 200 pf int, dreq 60 pf d15 to d8, udp, d7 to d0, ldp dmd15 to dmd8, udmdp 85 pf dmd7 to dmd0, ldmdp pin symbol c l c l : load capacitance c l measurement point measurement pin MB86604l c l v dd r l1 r l2 MB86604l measurement point measurement pin non-scsi pins scsi pins
14 MB86604l 4. ac characteristics (1) system clock * : the position number indicates the position in the waveform. note: in case that the internal clock frequency and the input clock frequency are the same (i.e. when using the divided-by-one mode), the clock pulse width (for h and l) must have at least 20 ns or longer. (2) system reset parameter symbol value unit position* min. max. clock cycle time (clk) t clk a 25.0 50.0 ns clock h pulse width t wckh b 10.0 ns clock l pulse width t wckl c 10.0 ns clock rise time t cr d 10.0 ns clock fall time t cf e 10.0 ns parameter symbol value unit min. max. reset l level pulse width t wrsl 4 t clk ns clk ba d e c 3.5 v 1.5 v t wckh t clk t cr t wckl t cf t wrsl reset
15 MB86604l (3) mpu interface (80 series) ? register write timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a4 to a0), bhe set up time wr l t sua a40ns address (a4 to a0), hold time wr h t ha b20ns cs0 set up time wr l t sucs0 c20ns cs0 hold time wr h t hcs0 d10ns wr l level pulse width t wwrl e70ns data set up time wr h t sud f40ns data hold time wr h t hd g10ns a c e b t ha d g f data a4 to a0 bhe cs0 wr d15 to d8, udp d7 to d0, ldp t sua t sucs0 t wwrl t hcs0 t hd t sud
16 MB86604l ? register read timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a4 to a0), bhe set up time rd l t sua a40ns address (a4 to a0), hold time rd h t ha b20ns cs0 set up time rd l t sucs0 c20ns cs0 hold time rd h t hcs0 d10ns rd l level pulse width t wrdl e70ns data output defined time rd l t vd f 70 ns data output disable time rd h t dz g10ns int signal clear time for int non-hold mode rd l t dl h 50 ns for int hold mode rd h t dl2 i n t clk + 50 ns a c e b d g f valid data a4 to a0 cs0 rd d15 to d8, udp h i int int t sua t sucs0 t wrdl t hcs0 t dz t vd t dl t dl2* t ha d7 to d0, ldp bhe *: t dl2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source. also, ??indicates the division ratio.
17 MB86604l ? register write timing (for external access) * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a0), bhe set up time wr l t suae a40ns address (a0), bhe hold time wr h t hae b20ns cs1 set up time wr l t sucs1 c20ns cs1 hold time wr h t hcs1 d10ns dma data bus output delay time wr l t vdmd e 70 ns dma data bus output undefined time wr h t wrdmd f10ns mpu data ? dma data bus output delay time t ddmd g 40 ns a c b d f e data a0 bhe cs1 wr d15 to d8, udp d7 to d0, ldp g dmd15 to dmd8, udmdp dmd7 to dmd0, ldmdp ! +, 6 ! " ) * +, - 4 5 6 valid data t suae t hae t hcs1 t sucs1 t vdmd t wrdmd t ddmd
18 MB86604l ? register read timing (for external access) * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a0), bhe set up time rd l t suae a40ns address (a0), bhe hold time rd h t hae b20ns cs1 set up time rd l t sucs1 c20ns cs1 hold time rd h t hcs1 d10ns mpu data bus output enable time rd l t zd e 70 ns mpu data bus output disable time rd h t dz f10ns dma data ? mpu data bus output delay time t dmdd g 40 ns a c b d f a0 bhe cs1 rd d15 to d8, udp d7 to d0, ldp e dmd15 to dmd8, udmdp dmd7 to dmd0, ldmdp valid data g t suae t hae t hcs1 t zd t dmdd t dz t sucs1 data
19 MB86604l (4) mpu interface (68 series) ? register write timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a4 to a0) set up time uds /lds l t sua a40ns address (a4 to a0) hold time uds /lds h t ha b20ns cs0 set up time uds /lds l t sucs0 c20ns cs0 hold time uds /lds h t hcs0 d10ns r/w set up time uds /lds l t surw e20ns r/w hold time uds /lds h t hrw f20ns uds /lds l level pulse width t wds g70ns data set up time uds /lds h t sud h40ns data hold time uds /lds h t hd i10ns a c g b d i h data a4 to a0 cs0 r/w d15 to d8, udp d7 to d0, ldp e f uds/lds t sua t sucs0 t surw t wds t sud t hd t hrw t hcs0 t ha
20 MB86604l ? register read timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a4 to a0) set up time uds /lds l t sua a40ns address (a4 to a0) hold time uds /lds h t ha b20ns cs0 set up time uds /lds l t sucs0 c20ns cs0 hold time uds /lds h t hcs0 d10ns r/w set up time uds /lds l t surw e20ns r/w hold time uds /lds h t hrw f20ns uds /lds l level pulse time t wds g70ns data output confirmation time uds /lds l t vd h 70 ns data output disable time uds /lds h t dz i10ns int signal clear time for int non-hold mode uds /lds l t dh j 50 ns for int hold mode uds /lds h t dh2 k n t clk + 50 ns a c g b d i valid data a4 to a0 cs0 r/w d15 to d8, udp d7 to d0, ldp e f uds/lds h j k int int t sua t sucs0 t surw t wds t vd t dh t dh2 t dz t hrw t hcs0 t ha *: t dh2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source. also, ??indicates the division ratio. *
21 MB86604l ? register write timing (for external access) * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a0) set up time uds /lds l t suae a40ns address (a0) hold time uds /lds h t hae b20ns cs1 set up time uds /lds l t sucs1 c20ns cs1 hold time uds /lds h t hcs1 d10ns r/w set up time uds /lds l t surw e20ns r/w hold time uds /lds h t hrw f20ns dma data bus output delay time uds /lds l t vdmd g 70 ns dma data bus output undefined time uds /lds h t dsdmd h10ns mpu data ? dma data bus output delay time t ddmd i 40 ns a b d f data a0 cs1 r/w uds/lds i ! " * +, - 5 6 ! ' ( ) * +, 2 3 4 5 6 valid data g h dmd15 to dmd8, udmdp dmd7 to dmd0, ldmdp d15 to d8, udp d7 to d0, ldp t suae t sucs1 t surw t vdmd t ddmd t dsdmd t hrw t hcs1 t hae c e
22 MB86604l ? register read timing (for external access) * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. address (a0) set up time uds /lds l t suae a40ns address (a0) hold time uds /lds h t hae b20ns cs1 set up time uds /lds l t sucs1 c20ns cs1 hold time uds /lds h t hcs1 d10ns r/w set up time uds /lds l t surw e20ns r/w hold time uds /lds h t hrw f20ns data output enable time uds /lds l t zd g 70 ns data output disable time uds /lds h t dz h10ns dma data ? mpu data bus output delay time t dmdd i 40 ns a c b d f e a0 cs1 r/w uds/lds i ! * +, 5 67 @ a valid data h dmd15 to dmd8, udmdp d15 to d8, udp d7 to d0, ldp g dmd7 to dmd0, ldmdp t zd t dz t dmdd t hrw t hcs1 t hae t suae t sucs1 t surw data
23 MB86604l (5) dma interface the dma access timing described in this section is not applicable in the following cases. during scsi input, when the data buffer is empty or when one byte is stored during scsi output, when the data buffer is full or when 31 bytes are stored when a parity error is detected (target) when an error which pauses the transfer occurs at the scsi interface ? 80 series handshake mode (a) write timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time dack l t akrq b 40 ns dreq h assert time (8 bit) dack h t akrq1 c 50 ns dreq h assert time (16 bit) dack h t akrq2 c 2 t clk + 40 ns iowr l assert time dack l t akwr d0ns dmbhe , dma0 set up time iowr l t suda e20ns dmbhe , dma0 hold time iowr h t hda f20ns iowr l level pulse width t wwrl g40ns dack h negate time iowr l t wrak1 h1 t clk ns iowr h t wrak2 i0ns input data set up time iowr h t sudmd j30ns input data hold time iowr h t hdmd k5ns
24 MB86604l e j f k data dreq dmd15 to dmd0 udmdp, ldmdp g h i d b a c dack dmbhe dma0 iowr t rqak t akrq t akwr t suda t wwrl t sudmd t hdmd t hda t wrak2 t akrq1/2 t wrak1
25 MB86604l (b) read timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time dack l t akrq b 40 ns dreq h assert time (8 bit) dack h t akrq1 c 50 ns dreq h assert time (16 bit) dack h t akrq2 c 2 t clk + 40 ns iord l assert time dack l t akrd d0ns dmbhe , dma0 set up time iord l t suda e20ns dmbhe , dma0 hold time iord h t hda f20ns iord l level pulse width t wrdl g40ns dack h negate time iord l t rdak1 h1 t clk ns iord h t rdak2 i0ns data output defined time iord l t vdmd j 40 ns data output hold time iord h t hdmd k10ns j f k valid data dreq dmd15 to dmd0 udmdp, ldmdp g h i d a c dack dmbhe dma0 iord t rqak t akrq t akrd t rdak1 t rdak2 t hda t wrdl t hdmd t vdmd t suda t akrq1/2 e b
26 MB86604l ? 68 series handshake mode (a) write timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time dack l t akrq b 40 ns dreq h assert time (8 bit) dack h t akrq1 c 50 ns dreq h assert time (16 bit) dack h t akrq2 c 2 t clk + 40 ns dmuds /dmlds l assert time dack l t akds d0ns dmr/w set up time dmuds /dmlds l t surw e20ns dmr/w hold time dmuds /dmlds h t hrw f20ns dmuds /dmlds l level pulse width t wdsl g40ns dack h negate time dmuds /dmlds l t dsak1 h1 t clk ns dmuds /dmlds h t dsak2 i0ns input data set up time dmuds /dmlds h t sudmd j30ns input data hold time dmuds /dmlds h t hdmd k5ns e j f k data dreq dmd15 to dmd0 udmdp, ldmdp g h i d b a c dack dmr/w dmuds/dmlds t rqak t akrq t akrq1/2 t dsak2 t hrw t hdmd t sudmd t surw t akds t dsak1 t wdsl
27 MB86604l (b) read timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time dack l t akrq b 40 ns dreq h assert time (8 bit) dack h t akrq1 c 50 ns dreq h assert time (16 bit) dack h t akrq2 c 2 t clk + 40 ns dmuds /dmlds l assert time dack l t akds d0ns dmr/w set up time dmuds /dmlds l t surw e20ns dmr/w hold time dmuds /dmlds h t hrw f20ns dmuds /dmlds l level pulse width t wdsl g40ns dack h negate time dmuds /dmlds l t dsak1 h1 t clk ns dmuds /dmlds h t dsak2 i0ns data output defined time dmuds /dmlds l t vdmd j 40 ns data output hold time dmuds /dmlds h t hdmd k10ns e j f k valid data dreq dmd15 to dmd0 udmdp, ldmdp g h i d b a c dack dmr/w dmuds/dmlds t rqak t akrq t akds t surw t vdmd t wdsl t hrw t hdmd t dsak2 t dsak1 t akrq1/2
28 MB86604l ? burst mode (80 series/68 series common) (a) data register access cycle time (8 bit) * : the position number indicates the position in the waveform. (b) data register access cycle time (16 bit) * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. data register access cycle time 1 t dcy1 at clk ns data register access cycle time 2 t dcy2 b3 t clk ns data register access cycle time 3 t dcy3 c4 t clk ns parameter symbol value unit base signal position* min. max. data register access cycle time 1 t dcy1 a4 t clk ns data register access cycle time 2 t dcy2 b3 t clk ns iowr/iord dmuds/dmlds a b c t dcy1 t dcy2 t dcy3 iowr/iord dmuds/dmlds a b t dcy1 t dcy2
29 MB86604l ? 80 series burst mode (a) write timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time iowr l t wrrq b 55 ns dreq l ? dreq h return time t rqlh c0ns iowr l assert time dack l t akwr d0ns dmbhe , dma0 set up time iowr l t suda e20ns dmbhe , dma0 hold time iowr h t hda f20ns iowr l level pulse width t wwrl g40ns dack h negate time iowr h t wrak h0ns input data set up time iowr h t sudmd i30ns input data hold time iowr h t hdmd j5ns e f data dreq dmd15 to dmd0 udmdp, ldmdp g h d a c dack dmbhe dma0 iowr j i t rqak t wrrq t rqlh t wrak t hda t hdmd t sudmd t wwrl t akwr t suda b
30 MB86604l (b) read timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time iord l t rdrq b 55 ns dreq l ? dreq h return time t rqlh c0ns iord l assert time dack l t akrd d0ns dmbhe , dma0 set up time iord l t suda e20ns dmbhe , dma0 hold time iord h t hda f20ns iord l level pulse width t wrdl g40ns dack h negate time iord h t rdak h0ns data output defined time iord l t vdmd i 40 ns data output hold time iord h t hdmd j10ns e f j valid data dreq dmd15 to dmd0 udmdp, ldmdp g h i d b ac dack dmbhe dma0 iord t rqak t rdrq t rqlh t rdak t hda t hdmd t vdmd t wrdl t suda t akrd
31 MB86604l ? 68 series burst mode (a) write timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time dmuds /dmlds l t dsrq b 55 ns dreq l ? dreq h return time t rqlh c0ns dmuds /dmlds l assert time dack l t akds d0ns dmr/w set up time dmuds /dmlds l t surw e20ns dmr/w hold time dmuds /dmlds h t hrw f20ns dmuds /dmlds l level pulse width t wdsl g40ns dack h negate time dmuds /dmlds h t dsak h0ns input data set up time dmuds /dmlds h t sudmd i30ns input data hold time dmuds /dmlds h t hdmd j5ns e f data dreq dmd15 to dmd0 udmdp, ldmdp g h d b a c dack dmr/w dmuds/dmlds j i t rqak t akds t dsrq t rqlh t dsak t hrw t hdmd t sudmd t surw t wdsl
32 MB86604l (b) read timing * : the position number indicates the position in the waveform. parameter symbol value unit base signal position* min. max. dack l assert time dreq h t rqak a0ns dreq l negate time dmuds /dmlds l t dsrq b 55 ns dreq l ? dreq h return time t rqlh c0ns dmuds /dmlds l assert time dack l t akds d0ns dmr/w set up time dmuds /dmlds l t surw e20ns dmr/w hold time dmuds /dmlds h t hrw f20ns dmuds /dmlds l level pulse width t wdsl g40ns dack h negate time dmuds /dmlds h t dsak h0ns data output defined time dmuds /dmlds l t vdmd i 40 ns data output hold time dmuds /dmlds h t hdmd j10ns e f j valid data dreq dmd15 to dmd0 udmdp, ldmdp g h i d b a c dack dmr/w dmuds/dmlds t rqak t dsrq t rqlh t dsak t hrw t wdsl t surw t vdmd t akds t hdmd
33 MB86604l (6) scsi interface (as initiator) ? asynchronous transfer mode (a) input timing (target ? initiator) *1: the position number indicates the position in the waveform. *2: the req h ? ack l time (t rqak2 ) is compared with (t rqakh + t akrql + t rqak1 ) and the longer value is chosen. note: the input timing definition is not applied in the following cases. ? when the data register is full in the data phase ? when the final byte is being transferred parameter symbol value unit base signal position* 1 min. max. req h negate time ack l t akrqh a0ns ack h negate time req h t rqakh b 60 ns req l assert time ack h t akrql c10ns input data set up time req l t sudb d10ns input data hold time req l t hdb e20ns ack l assert time 1 req l t rqak1 f 40 ns ack l assert time 2 * 2 req h t rqak2 g 3 t clk + 40 ns a f data db7 to db0 dbp g e req ack c b d t akrqh t rqakh t akrql t rqak1 t rqak2 t hdb t sudb
34 MB86604l (b) output timing (initiator ? target) *1: the position number indicates the position in the waveform. *2: s value is based on the asychronous set up time setting register (address 17h). note: the output timing definitions are not applied when the data register is empty in the data phase. parameter symbol value unit base signal position* 1 min. max. req h negate time ack l t akrqh a0ns ack h negate time req h t rqakh b60ns req l assert time ack h t akrql c10ns time from output data valid to ack l assert * 2 t dbak d s ? t clk C 10 ns output data hold time req h t hdb e2 t clk ns ack l assert time req l t rqak1 f40ns a f valid data db7 to db0 dbp * e req ack c b d % & ' ( valid data d t rqak2 t rqak1 t akrql t rqakh t akrqh t dbak t hdb t dbak *: the req h ? ack l time (t rqak2 ) is defined by either longer of (t rqakh + t akrql + t rqak1 ) or (t hdb + t dbak ) (see the output timing waveform).
35 MB86604l ? synchronous transfer mode (a) req /ack signal period *1: the position number indicates the position in the waveform. *2: a and n values are based on the transfer period register (address 0dh) setting. parameter symbol value unit base signal position* 1 min. max. ack assert time * 2 t akap a a ? t clk C 12 ns ack negate time * 2 t aknp b n ? t clk + 2 ns req assert time t rqap c20ns req negate time t rqnp d20ns req input cycle time 1 t rqcy1 e1 t clk ns req input cycle time 2 t rqcy2 f3 t clk ns a e req ack b f c d t akap t aknp t rqnp t rqap t rqcy1 t rqcy2
36 MB86604l (b) input timing (target ? initiator) * : the position number indicates the position in the waveform. (c) input timing (target ? initiator) *1: the position number indicates the position in the waveform. *2: a and n values are based on the transfer period register (address 0dh) setting. parameter symbol value unit base signal position* min. max. input data set up time req l t sudb a5ns input data hold time req l t hdb b15ns parameter symbol value unit base signal position* 1 min. max. time from output data valid to ack l assert * 2 t dbak a n ? t clk + 2 ns output data hold time * 2 ack l t hdb b a ? t clk C 12 ns req db7 to db0 dbp b data data a b a t hdb t sudb t hdb t sudb ack db7 to db0 dbp b valid data valid data ! ( ) * +, 3 4 5 6 a b a ! ) * +, 4 5 6 ! " # $ % ( ) * +, - . / 0 3 4 5 6 t dbak t hdb t hdb t dbak
37 MB86604l (7) scsi interface (as initiator) ? asynchronous transfer mode (a) input timing (initiator ? target) *1: the position number indicates the position in the waveform. *2: the req l ? req l time (t akrq2 ) is compared with (t akrqh + t rqakh + t akrq1 ) and the longer value is chosen. note: the input timing definition is not applied in the following cases. ? when the data register is full in the data phase ? when the final byte is being transferred parameter symbol value unit base signal position* 1 min. max. ack l assert time req l t rqakl a0ns req h negate time ack l t akrqh b 60 ns ack h negate time req h t rqakh c0ns input data set up time ack l t sudb d10ns input data hold time ack l t hdb e20ns ack l assert time 1 ack h t akrq1 f 40 ns ack l assert time 2 * 2 ack h t alrq2 g 3 t clk + 40 ns a data db7 to db0 dbp g e req ack f c d b t akrq2 t rqakl t akrqh t rqakh t akrq1 t hdb t sudb
38 MB86604l (b) output timing (target ? initiator) *1: the position number indicates the position in the waveform. *2: s value is based on the asychronous set up time setting register (address 17h). note: the output timing definitions are not applied when the data register is empty in the data phase. parameter symbol value unit base signal position* 1 min. max. ack l assert time req l t rqakl a0ns req h negate time ack l t akrqh b60ns ack h negate time req h t rqakh c0ns time from output data valid to req l assert * 2 t dbrq d s ? t clk C 10 ns output data hold time ack l t hdb e2 t clk ns req l assert time ack h t akrq1 f40ns a valid data e req ack f c d b d * valid data db7 to db0 dbp ! ( ) * +, 3 4 5 67 > ? @ a t akrq2 t akrq1 t rqakh t rqakl t hdb t dbrq t dbrq t akrqh *: the ack l ? req l time (t akrq2 ) is defined by either longer of (t akrqh + t rqakh + t akrq1 ) or (t hdb + t dbrq ).
39 MB86604l ? synchronous transfer mode (a) req /ack signal period *1: the position number indicates the position in the waveform. *2: a and n values are based on the transfer period register (address 0dh). see (8) for more setting values. parameter symbol value unit position* 1 min. max. req assert time * 2 t rqap a a ? t clk C 12 ns req negate time * 2 t rqnp b n ? t clk + 2 ns ack assert time t akap c20 ns ack negate time t aknp d20 ns ack input cycle time 1 t akcy1 e1 t clk ns ack input cycle time 2 t akcy2 f3 t clk ns a t rqap e req ack t akcy1 b f t akcy2 t rqnp c t akap d t aknp
40 MB86604l (b) input timing (initiator ? target) * : the position number indicates the position in the waveform. (c) output timing (target ? initiator) *1: the position number indicates the position in the waveform. *2: a and n values are based on the transfer period register (address 0dh). see (8) for more setting values. parameter symbol value unit base signal position* min. max. input data set up time ack l t sudb a5ns input data hold time ack l t hdb b15ns parameter symbol value unit base signal position* 1 min. max. time from output data valid to req l assert * 2 t dbrq a n ? t clk + 2 ns output data hold time * 2 req l t hdb b a ? t clk C 12 ns ack db7 to db0 dbp t hdb b t hdb data data a t sudb b a t sudb req db7 to db0 dbp b valid data valid data ! ( ) * + a b a ! ) * + ! " # $ % ( ) * + t dbrq t hdb t hdb t dbrq
41 MB86604l (8) a/n/s values in the scsi interface timing specification ? transfer period register (address 0dh) and a/n values note: the a and n values set in the register are the assert period and the negate period respectively (unit is clock cycles) for the ac characteristics, a/n use numerals. ? asynchronous setup time register (address 17h) setting and the s value. note: the s (setup time) value established in the set up time register during asynchronous data transfers indicates the time from setting data in the data bus until the req /ack signals are asserted. for the ac characteristics, s uses numerals. transfer period register an transfer period register an bit 4 bit 3 bit 2 bit 1 bit 0 bit 4 bit 3 bit 2 bit 1 bit 0 00001prohibitprohibit10001 9 8 00010 1 1 10010 9 9 00011 2 1 10011 10 9 00100 2 2 10100 10 10 00101 3 2 10101 11 10 00110 3 3 10110 11 11 00111 4 3 10111 12 11 01000 4 4 11000 12 12 01001 5 4 11001 13 12 01010 5 5 11010 13 13 01011 6 5 11011 14 13 01100 6 6 11100 14 14 01101 7 6 11101 15 14 01110 7 7 11110 15 15 01111 8 7 11111 16 15 10000 8 8 00000 16 16 asynchronous setup time register s asynchronous setup time register s bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0001 1 1001 9 0010 2 1010 10 0011 3 1011 11 0100 4 1100 12 0101 5 1101 13 0110 6 1110 14 0111 7 1111 15 1000 8 0000 16
42 MB86604l n list of registers 1. basic control registers (for write) 2. basic control registers (for read) note: x indicates data is undefined. (0 or 1). address register name bit assignment hex. a4 a3 a2 a1 a0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 00000output data register (first) do7do6do5do4do3do2do1do0 01 00001 output data register (second) do15 do14 do13 do12 do11 do10 do9 do8 02 00010direct control register dc7 0 0 do4 0000 03 00011(reserved) 0 0 0 00000 04 00100sel/r esel id register si7 0 0 0 0 si2 si1 si0 05 00101comm and register cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 06 00110data block register (msb) bl15bl14bl13bl12bl11bl10bl9 bl8 07 00111data block register (lsb) bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 08 01000data byte register (msb) by23by22by21by20by19by18by17by16 09 01001data byte register by15by14by13by12by11by10by9 by8 0a01010 data byte register (lsb) by7 by6 by5 by4 by3 by2 by1 by0 mc byte register 0b01011dia gnostic control register dg7 dg6 dg5 0 dg3 dg2 dg1 dg0 0c01100transfer mode register tm7 0 0 00000 0d01101transfer period register 0 0 0 tp4 tp3 tp2 tp1 tp0 0e01110transfer offset register 0 0 0 to4 to3 to2 to1 to0 0f01111window address register wa7 wa6 0 0 wa3 wa2 wa1 wa0 address register name bit assignment hex. a4 a3 a2 a1 a0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 00000i nput data register (first) di7 di6 di5 di4 di3 di2 di1 di0 01 00001i nput data register (second) di15 di14 di13 di12 di11 di10 di9 di8 02 00010spc status register ss7 ss6 ss5 ss4 x ss2 ss1 ss0 03 00011nexus status register ns7 ns6 ns5 x x ns2 ns1 ns0 04 00100interrupt status register is7 is6 is5 is4 is3 is2 is1 is0 05 00101comm and step register cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 06 00110data block register (msb) bl15bl14bl13bl12bl11bl10bl9 bl8 07 00111data block register (lsb) bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 08 01000data byte register (msb) by23by22by21by20by19by18by17by16 09 01001data byte register by15by14by13by12by11by10by9 by8 0a01010 data byte register (lsb) by7 by6 by5 by4 by3 by2 by1 by0 mc byte register 0b01011 scsi control signal status register sc7 sc6 sc5 sc4 sc3 sc2 sc1 sc0 0c01100transfer mode register tm7 xxxxxxx 0d01101transfer period register x x x tp4 tp3 tp2 tp1 tp0 0e01110transfer offset register x x x to4 to3 to2 to1 to0 0f01111modified byte register x x mb5bm4mb3mb2mb1mb0
43 MB86604l 3. initial setting window (for read/write) 4. mcs buffer window address register name bit assignment hex. a4 a3 a2 a1 a0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10 10000clock conversion setting cc7cc6cc5cc4cc3cc2cc1cc0 11 10001self id setting 00000oi2oi1oi0 12 10010response mode setting am7am6am5am4 0 0 am1am0 13 10011selection/reselection m ode setting sm7 sm6 sm5 sm4 sm3 sm2 sm1 sm0 14 10100selection/reselection retry setting sr7sr6sr5sr4sr3sr2sr1sr0 15 10101 selection/reselection timeout setting st7st6st5st4st3st2st1st0 16 10110req/ack timeout setting rt7rt6rt5rt4rt3rt2rt1rt0 17 10111asynchronous setup time setting 0000at3at2at1at0 18 11000parity error detection setting pe7pe6pe5pe4pe3 0 pe1pe0 19 11001interrupt enable setting ie7 0 ie5 ie4 ie3 ie2 ie1 ie0 1a11010group 6/7 command length settinggl7gl6gl5gl4gl3gl2gl1gl0 1b11011dma system setting 0 0 dm5md4 0 0 0 0 1c11100automatic operation mode setting om7om6om5om4om3om2om1om0 1d11101spc timeout setting to7to6to5to4to3to2to1to0 1f 11111device revision indication rv7rv6rv5rv4rv3rv2rv1rv0 address for write for read hex. a4 a3 a2 a1 a0 1010000 send mcs buffer receive mcs buffer 1110001 send mcs buffer receive mcs buffer 1210010 send mcs buffer receive mcs buffer 1310011 send mcs buffer receive mcs buffer 1410100 send mcs buffer receive mcs buffer 1510101 send mcs buffer receive mcs buffer 1610110 send mcs buffer receive mcs buffer 1710111 send mcs buffer receive mcs buffer 1811000 send mcs buffer receive mcs buffer 1911001 send mcs buffer receive mcs buffer 1a11010 send mcs buffer receive mcs buffer 1b11011 send mcs buffer receive mcs buffer 1c11100 send mcs buffer receive mcs buffer 1d11101 send mcs buffer receive mcs buffer 1e11110 send mcs buffer receive mcs buffer 1f11111 send mcs buffer receive mcs buffer
44 MB86604l 5. user program memory window address for write for read hex. a4 a3 a2 a1 a0 1010000 user program memory user program memory 1110001 user program memory user program memory 1210010 user program memory user program memory 1310011 user program memory user program memory 1410100 user program memory user program memory 1510101 user program memory user program memory 1610110 user program memory user program memory 1710111 user program memory user program memory 1811000 user program memory user program memory 1911001 user program memory user program memory 1a11010 user program memory user program memory 1b11011 user program memory user program memory 1c11100 user program memory user program memory 1d11101 user program memory user program memory ie11110 user program memory user program memory 1f11111 user program memory user program memory
45 MB86604l n list of commands spc commands can be specified in the command register or the user program memory and divided into the following main groups. ? sequential commands commands that perform a consecutive (including phase transitions) sequence operation. can only be specified in the command register (1-byte). ? discrete commands commands which perform operations from disassembled sequential commands. can be specified in the command register (1-byte command) or the user program memory (1/2-byte command). ? special commands can only be specified in the user program memory (1/2-byte command). 1. initiator commands (1) sequential commands no command code operand (for program) command name 1 00h00000000 (not possible) select & cmd 2 01h00000001 (not possible) select & 1-msg & cmd 3 02h00000010 (not possible) select & n-byte-msg & cmd 4 03h00000011 (not possible) select & 1-msg 5 04h00000100 (not possible) select & n-byte-msg 6 05h00000101 (not possible) s end n-byte-msg 7 06h00000110 (not possible) s end n-byte-cmd 8 07h00000111 (not possible) receive n-byte-msg
46 MB86604l (2) discrete commands no command code operand (for program) command name 9 08h00001000 select 1009h00001001 select with atn 110ah00001010 set atn 120bh00001011 reset atn 130ch00001100 set ack 140dh00001101 reset ack 1510h00010000 s end data from mpu 1611h00010001 s end data from dma 1712h00010010 receive data to mpu 1813h00010011 receive data to dma 1914h00010100 s end data from mpu padding 2015h00010101 s end data from dma padding 2116h00010110 receive data to mpu padding 2217h00010111 receive data to dma padding 2318h00011000address of msg sent s end 1-msg 2419h00011001address of msg sent s end 1-msg with atn 251ah00011010save address of msg receive msg 261bh00011011address of cmd sent s end cmd 271ch00011100save address of statusreceive status
47 MB86604l 2. target commands (1) sequential commands no command code operand (for program) command name 1 20h00100000 (not possible) reselect & 1-msg 2 21h00100001 (not possible) reselect & n-byte-msg 3 22h00100010 (not possible) reselect & 1-msg & terminate 4 23h00100011 (not possible) reselect & 1-msg & link-terminate 5 24h00100100 (not possible) terminate 6 25h00100101 (not possible) link-terminate 7 26h00100110 (not possible) disc onnect-sequence 8 27h00100111 (not possible) send n-byte-msg 9 28h00101000 (not possible) receive n-byte-cmd 1029h00101001 (not possible) receive n-byte-msg 112ah00101010 (not possible) reselect & n-byte-msg & terminate 122bh00101011 (not possible) reselect & n-byte-msg & link-terminate 132ch00101100 (not possible) disc onnect-sequence 2
48 MB86604l (2) discrete commands 3. common commands no command code operand (for program) command name 1430h00110000 reselect 1531h00110001 set req 1632h00110010 reset req 1733h00110011 disc onnect 1834h00110100 send data from mpu 1935h00110101 send data from dma 2036h00110110 receive data to mpu 2137h00110111 receive data to dma 2238h00111000address of msg sent send 1 msg 2339h00111001save address of msg receive msg 243ah00111010s end-status address send status 253bh00111011save address of cdb receive cmd no command code operand (for program) command name 1 40h01000000 (not possible) software r eset 2 41h01000001 (not possible) transfer r eset 3 42h01000010 (not possible) scsi r eset 4 43h01000011 (not possible) set up reg 5 44h01000100 (not possible) init diag start 6 45h01000101 (not possible) targ diag start 7 46h01000110 (not possible) diag end 8 47h01000111 (not possible) command pause 9 48h01001000 (not possible) set rst 1049h01001001 (not possible) reset rst
49 MB86604l 4. programmable commands the user program is stored in the user program memory and begins operation when the user program head address is written in the command register. programmable commands are composed of discrete and special commands and have a command length of one (1) or two (2) bytes. ? command field assign command type command code (1st byte) operand (2nd byte) discrete commands message, command, or status phases send command memory address of the data to be sent. message, command, or status phases receive command memory address of received data being stored. data phase receive/send command or do not perform transfer command special commands and command data for and operation or memory address of data for and operation. test and command data for and operation or memory address of data for and operation. compare command data for compare operation or memory address of data for compare operation. conditional branch command jump head address move command memory address to be moved. stop command user status code nop command
50 MB86604l n system configuration example 1. 80-series, separate bus type MB86604l db7 to 0 dbp ack atn req msg c/d i/o bsy sel rst clk reset mode int tmout cs0 cs1 a4 to a0 d15 to d0 udp ldp bhe rd wr dmd15 to 0 udmdp ldmdp dreq dack dmbhe iord iowr dma0 tp dma controller address data buffer memory dma bus data bus address bus address decoder mpu reset circuit oscillation circuit scsi bus
51 MB86604l 2. 80-series, common bus type MB86604l db7 to 0 dbp ack atn req msg c/d i/o bsy sel rst clk reset mode int tmout cs1 cs0 a4 to a0 d15 to d0 udp ldp bhe rd wr dmd15 to 0 udmdp ldmdp dreq dack dmbhe iord iowr dma0 tp dma controller address decoder mpu reset circuit oscillation circuit address bus data bus dma bus scsi bus
52 MB86604l 3. 68-series, separate bus type MB86604l db7 to 0 dbp ack atn req msg c/d i/o bsy sel rst clk reset mode int tmout cs0 cs1 a4 to a1 d15 to d0 udp ldp r/w uds lds dmd15 to 0 udmdp ldmdp dreq dack dmr/w dmuds dmlds dma0 tp dma controller address data buffer memory dma bus data bus address bus address decoder mpu reset circuit oscillation circuit a0 scsi bus
53 MB86604l 4. 68-series, common bus type MB86604l db7 to 0 dbp ack atn req msg c/d i/o bsy sel rst clk reset mode int tmout cs1 cs0 a4 to a1 d15 to d0 udp ldp r/w uds lds dmd15 to 0 udmdp ldmdp dreq dack dmr/w dmuds dmlds dma0 tp dma controller address decoder mpu reset circuit oscillation circuit address bus data bus a0 dma bus scsi bus
54 MB86604l n ordering information part number package remarks MB86604lpfv 100 pin plastic lqfp (fpt-100p-m05)
55 MB86604l n package dimension 100-pin plastic lqfp (fpt-100p-m05) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. dimensions in mm (inches) (mounting height)
56 MB86604l fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9702 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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